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Verilog is the hardware description language behind a huge share of the world's digital chips, and Icarus Verilog is the open source simulator that lets you run it without vendor licenses. Instead of instructions executing in order, you describe registers, wires, and always blocks that respond to clock edges, then drive them from a testbench and observe the waveform of values over simulated time. Icarus (iverilog plus its vvp runtime) is the standard choice in university digital design labs and hobbyist FPGA workflows targeting boards like the iCE40. This page compiles your modules and testbench and streams $display output live in the terminal, so you can debug a counter or ALU design straight from the browser.
module counter(
input wire clk,
input wire rst,
output reg [3:0] count
);
always @(posedge clk or posedge rst) begin
if (rst)
count <= 4'd0;
else
count <= count + 4'd1;
end
endmodule
module tb;
reg clk = 0;
reg rst = 1;
wire [3:0] count;
counter uut (.clk(clk), .rst(rst), .count(count));
always #5 clk = ~clk;
initial begin
$display("time | rst count");
#12 rst = 0;
repeat (6) begin
@(posedge clk);
#1 $display("%4t | %b %d", $time, rst, count);
end
$display("Counter reached %0d, stopping.", count);
$finish;
end
endmoduleIcarus Verilog is the workhorse of digital logic coursework: counters, finite state machines, ALUs, and pipeline stages are all assigned as module-plus-testbench pairs exactly like the example above. FPGA hobbyists in the open source toolchain community simulate designs here before synthesizing with yosys, and students preparing for computer engineering exams verify blocking versus nonblocking assignment behavior interactively. It is also convenient for interview preparation at hardware companies, where whiteboard RTL questions can be sanity-checked in seconds without installing a simulator.
Use system tasks in your testbench: $display prints a line immediately, $monitor prints whenever listed signals change, and $time reports simulation time. Output streams live into the terminal as simulation advances. Always end with $finish, otherwise a free-running clock generator keeps the simulation alive until the sandbox time limit stops it.
Your code is compiled with Icarus Verilog and executed by its vvp runtime, with solid support for Verilog-2001 and the commonly used parts of Verilog-2005, including generate blocks and named port connections. SystemVerilog support is partial, so classwork written in plain Verilog is the safest fit; advanced SV verification features like classes will not compile.
Not graphically; the environment is a text terminal, so the usual workflow of dumping a VCD file with $dumpfile and opening it in GTKWave does not apply. The practical substitute is $monitor, which logs every signal change with timestamps, giving you a textual waveform that is usually sufficient for homework-scale designs.
main.vtext/x-verilogno standard input constructmodule main;
initial begin
$display("Hello from Verilog!");
$finish;
end
endmodule